1. Technical Field
The invention relates to nano-scale devices and the fabrication of nano-scale devices. In particular, the invention relates to reducing a size, spacing and/or pitch dimension of features in a nano-scale device or structure.
2. Description of Related Art
A consistent trend in semiconductor technology since its inception is toward smaller and smaller device dimensions and higher and higher device densities. As a result, an area of semiconductor technology that recently has seen explosive growth and generated considerable interest is nanotechnology. Nanotechnology is concerned with the fabrication and application of so-called nano-scale structures, structures having dimensions that are often 50 to 100 times smaller than conventional semiconductor structures. Nano-imprinting lithography is a technique used to fabricate nano-scale structures.
Nano-imprinting lithography uses a mold to imprint nano-scale structures on a substrate using a top-down scaling technique. A mold typically contains a plurality of protruding and/or recessed regions or ‘features’ having some nano-scale dimensions. Typically, the features of the mold are imprinted on a substrate coated with a viscous polymer precursor. Thus, the features on the mold are complementary to the desired device features (e.g., nanowires). The dimensions achieved for the features on the mold, such as nanowire width and pitch, ultimately affect the dimensions achieved for the desired device features. A mold can be fabricated using electron beam (e-beam) lithography or x-ray lithography to define a pattern and a dry etching process, typically reactive ion etching (RIE), to create features from the pattern in the mold in the nano-scale and/or micro-scale range(s). Various lithography steps are repeated in a serial manner in an attempt to achieve smaller dimensions. The current e-beam or x-ray lithographies are limited in yielding molds with a nanowire width less than about 15 nm and a nanowire pitch less than about 30 nm. In addition, the e-beam and x-ray lithographic processes are very slow processes rendering such serial repetition of steps undesirable for achieving smaller dimensions. Moreover, significant improvements in the conventional e-beam and x-ray lithographic steps are necessary to achieve a feature pitch dimension less than about 30 nm and/or a feature width or a feature spacing of less than about 15 nm. Such improvements are not cost effective since an inherent limitation in these lithographic processes restricts achieving features sizes smaller than about 15 nm. It has been reported that feature sizes of approximately 10 nm are achievable with these conventional processes. However, usually there is a trade-off between the line-width and the line-spacing (i.e., pitch) and feature quality. Thus, these dimensions are estimates of the limits on the feature size and spacing achievable conventionally.
Accordingly, it would be desirable to fabricate nano-scale devices or structures with greater nano-scale feature density at potentially lower cost than conventionally fabricated with e-beam or x-ray lithography and RIE. Such fabricated nano-scale devices would solve a long-standing need in the developing area of a “top-down” fabrication approach in nanotechnology.